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SE1770DO

Adds capabilities for GPON, EPON, 10GPON testing. 2 Filter inputs and outputs accessible from the faceplate. A Burst control signal generator for asymmetric PON CDR mode for the DSO + FPGA

Electrical Specifications

PPG

Error Detector Sensitivity
30 mVp-p @ bitrates >12 Gb/s | 50 mVp-p @ bitrates >12 Gb/s
Error Detector Maximum Input
1200 mVpp Diff
Error Detector Phase Margin
5 ps
Output Return Loss (10-25 GHz)
<-8 dB
Output Return Loss up to 10 GHz
<-10 dB
TX Skew control resolution
N/A
TX Skew control range
N/A
Rise/Fall Time (20-80%)
14 ps
Random Filter RMS
<300 fs @25.78125 Gb/s
Equalizing Filter Spacing
1 UI
Pre-Emphasis Resolution
10 steps
Pre-Emphasis
10 dB
Patterns
PRBS 7/9/15/23/31 User Pattern 80 bits
TX Amplitude Differential
250-800 mV
Bit Rates
1 - 16 Gbps or 1 - 30 Gbps

ED

Conversion Gain @ 1310 nm
450 W/V
Overload
+2 dBm
Sensitivity @ 850 nm
-19 dBm
Sensitivity @ 1310 nm
-19 dBm
Wavelength Range
750 - 1650 nm
CTLE Support
Auto-tune
Reference clock output rate
6.25 - 750 MHz
Reference clock output amplitude
550 - 850 mVp-p
TX/RX connectors
2.92 mm connectors
Vertical Scan Resolution
8 Bits
Phase Scan Resolution
6 Bits

DSO

Input Bandwidth
32 GHz or 50 GHz
Hardware Filter
10.3125G Filter 3 dB loss: 7.73GHz
Hardware Filter
2.5G Filter 3 dB Loss: 1.87 GHz
Hardware Filter
1.25G Filter 3 dB Loss: 0.93 GHz
Hardware Filter
Shape: Bessel Thomson 4th order
Memory Depth
256k samples
Temperature range
0-65 °C
Power Requirements
100 to 240 V - 50/60 Hz
Spurious-Free Dynamic Range
-58 dBc at 10 GHz, 500 mVpp, 1 GS/s | -53 dBc at 30 GHz, 500 mVpp, 1 GS/s
PRBS Pattern Capture
up to PN13
Data Format Support
NRZ / PAM4
Amplitude Error
5 mV
Intrinsic jitter (excluding DDI)
200 fs
Clock Input Impedance
500 Ω
Clock Input Amplitude
200 - 1000 mV
Clock Input Range
50 - 125 MHz
Connector Type
FC
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