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Products
SE1746
The SE1746 enhances its functionality by adding support for GPON, EPON, and 10GPON testing. It features two filter inputs and outputs accessible directly from the faceplate, providing easy connectivity. Additionally, it includes a burst control signal generator designed for asymmetric PON CDR mode, leveraging the combined capabilities of the Digital Sampling Oscilloscope (DSO) and FPGA for advanced signal management and testing.
Electrical Specifications
Bit Rates | PAM4: 18.5 - 29 GBaud / 37 - 61 GBaud NRZ: 18.5 ? 29 Gbps / 37 - 61 Gbps |
TX Amplitude Differential | 0 - 1200 mVpp at High Rates & 0 ? 1800 mVpp at Low Rates |
Patterns | PRBS 7/9/11/13/15/16/23/31/58/9.4 SQ16, SQ32, LIN, CJT, JP0838, SSPRQ, User Defined |
TX Amplitude Adjustment | Steps of 1 mV |
Pre-emphasis resolution | 1000 steps |
Pre- / Post-emphasis | 6 dB |
Equalizing Filter Spacing | 1 UI |
Random Jitter RMS? | < 290 fs |
Rise/ Fall Time (20?80%)? | < 10 ps |
Coding | Gray coding supported |
FEC (up to 800G) | KP (100G, 400G) |
KR (100G) | |
Output Return Loss up to 10 GHz | < -15 dB |
Output Return Loss (16-25 GHz) | < -10 dB |
Error Detector input range | 50 - 800 mV differential |
TX/RX connectors | 4x 8 channel M-SMPM foot print on front channel |
Reference clock | Reference clock |
Reference Clock Output | 156.25 MHz |
Clean Clock | Used as high frequency trigger in clean (jitter disabled) or jitter mode: Reference Clock multiplied by an integer ranging from 2 to 30 |
Diff. Input Return Loss | Better than 10 dB |
Eye monitor resolution | 8 bits horizontal across 2 UI / 9 bits vertical |
Clock Input Range | Up to 4.4 GHz |
Clock Input Amplitude | 200 - 1000 mV |
Input Impedance | 50 Ω |
Ambient Temperature | 0 - 75 °C |
Power | 110 V, 1.4 A or 220 V, 0.9 A ? 50/60 Hz |
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