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Products
SE1706L
The SE1706L is a fully automated network loopback verifier designed for 25G and 100G systems, ensuring signal fidelity and validating the CMIS protocol compliance of SFP28 and QSFP28 loopbacks. Tailored for production lines and deployment scenarios, it delivers fast diagnostics and reliable performance for high-bandwidth network infrastructures.
Electrical Specifications
Parameter | Specifications |
|---|---|
Bit Rates | 8.5-15 and 21-30 Gbps |
Bit Rate Accuracy | Better than ±20 ppm? |
Data Format | NRZ |
Pattern | PRBS 7, 9, 15, 23, 31, and User Defined Pattern 16 bits@10G & 40 bits@25G |
TX Amplitude Differential | 200 - 800 mV² |
TX Amplitude Adjustment | Steps of 200 mV |
Pre-Emphasis | 6 dB |
Pre-Emphasis Resolution | 20 steps |
Equalizing Filter Spacing | - |
Total Jitter pk-pk @10G | 10 ps (typical) |
Total Jitter pk-pk @25G | 12 ps (typical) |
Rise/Fall Time (20?80%) @25G | < 14 ps? |
Sinusoidal Phase Modulation | - |
Sinusoidal Jitter Frequency | - |
Random Jitter in Phase Modulation | - |
Output Return Loss up to 10GHz | -15 dB |
Output Return Loss (16-25GHz) | -8 dB |
TX Skew Control Range | - |
Lane to Lane Skew Resolution | - |
Error Detector Phase Margin | 5 ps |
Error Detector Input Amplitude | 110-1050 mVpp @11G, 1200 mVpp @25G |
Error Detector Maximum Input | 1200mV Diff |
Error Detector Input Sensitivity | 30 mVpp @ 10.3125G / 50 mVpp @ 28G |
Phase Scan Resolution | 7 bits |
Vertical Scan Resolution | 8 bits |
Input CTLE Dynamic Range | 10 dB |
Reference Clock Output | Rate/32 for 8.5-15G and Rate/80 for 21-30G |
Reference Clock Output Amplitude | 550 - 850 mVpp |
Reference Clock Input | Rate/32 for 8.5-15G and Rate/80 for 21-30G |
Reference Clock Input Amplitude | 300 - 1900 mVpp |
Clock Data Recovery | Rate/N (user selectable from 8 and 16) |
Power Requirement | 21.5 Watt |
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