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SE1706-JA
The SE1706-JA is a 4x30 Gbps BERT designed for NRZ signal generation, essential for 100 Gb measurements. It is ideal for production testing of systems, components, and Electro-Optical Modules. The device supports test patterns in compliance with IEEE and OIF standards. Additional features include signal-to-noise ratio (SNR) analysis, histogram measurements, and built-in transmitter and receiver equalizers.
Electrical Specifications
Bit Rate | 8.5-15 & 21-30 Gbps |
Data Format | NRZ |
Pattern | PRBS 7, 9, 15, 23, 31, and User Defined Pattern 16 bits@10G & 40 bits@25G |
TX Amplitude Differential | 100-2000 mV* |
TX Amplitude Adjustment | 5 mV/step |
Pre-Emphasis | - |
Pre-Emphasis Resolution | - |
Equalizing Filter Spacing | - |
Total Jitter pk-pk @10G | 10 ps (typical) |
Total Jitter pk-pk @25G | 12 ps (typical) |
Rise/Fall Time (20?80%) @25G | < 14 ps** |
Sinusoidal Phase Modulation | 30 ps |
Sinusoidal Jitter Frequency | 0.1 to 80 MHz |
Random Jitter in Phase Modulation | 30 ps (composite) |
Output Return Loss up to 10GHz | <-12dB |
Output Return Loss (16-25GHz) | <-8dB |
TX Skew Control Range | 100ps |
Lane to Lane Skew Resolution | 0.5 ps |
Error Detector Phase Margin | 5 ps |
Error Detector Input Amplitude | 110-1050 mVpp @11G, 1200 mVpp @25G |
Error Detector Maximum Input | 1200 mV Diff |
Error Detector Input Sensitivity | 30 mVpp @ 10.3125G / 50 mVpp @ 28G |
Phase Scan Resolution | 7 bits |
Vertical Scan Resolution | 8 bits |
Input CTLE Dynamic Range | 10 dB |
Reference Clock Output | Rate/32 for 8.5-15G and Rate/80 for 21 - 30G |
Reference Clock Output Amplitude | 550-850 mVpp |
Reference Clock Input | Rate/32 for 8.5-15G and Rate/80 for 21 - 30G |
Reference Clock Input Amplitude | 300-1900 mVpp |
Clock Data Recovery | Rate/N |
TX/RX and Clock Connectors in ATE | SMPM-RA |
Power Requirement | 1.9A @12 V |
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